1. Technical Field
The present invention relates generally to an improved data processing system and in particular to a method and apparatus for detecting a hang condition in a simultaneous multi-threading processor. Still more particularly, the present invention relates generally to an improved method and apparatus for intelligent hang detection taking into account shared resource contention/blocking.
2. Description of Related Art
Modern processors commonly use a technique known as pipelining to improve performance. Pipelining is an instruction execution technique that is analogous to an assembly line. Consider that instruction execution often involves sequential steps of fetching an instruction from memory, decoding the instruction into its respective operation and operand(s), fetching the operands of the instruction, applying the decoded operation on the operands (herein simply referred to as “executing” the instruction), and storing the result back in memory or in a register. Pipelining is a technique wherein the sequential steps of the execution process are overlapped for a sub-sequence of the instructions. For example, while the processor is storing the results of a first instruction of an instruction sequence, the processor simultaneously executes the second instruction of the sequence, fetches the operands of the third instruction of the sequence, decodes the fourth instruction of the sequence, and fetches the fifth instruction of the sequence. Pipelining can thus decrease the execution time for a sequence of instructions.
Another technique for improving performance involves executing two or more instructions from the same code stream in parallel, i.e., simultaneously. Processors that utilize this technique are generally referred to as superscalar processors. Such processors may incorporate an additional technique in which a sequence of instructions may be executed out of order. Results for such instructions must be reassembled upon instruction completion such that the sequential program order or results are maintained. This system is referred to as out-of-order issue with in-order completion.
Yet another technique for improving performance involves executing two or more code streams (called “processes” or “threads”) simultaneously. While one thread is stalled waiting on a dependency or high latency operation (such as fetch from memory or an IO device), the other thread can make use of the otherwise idle circuits in the core (e.g. execution units). This is referred to as Simultaneous Multi-Threading (SMT) or by others in the industry as “hyperthreading.”
The ability of a superscalar processor to execute two or more instructions simultaneously depends upon the particular instructions being executed. Likewise, the flexibility in issuing or completing instructions out-of-order can depend on the particular instructions to be issued or completed. There are three types of such instruction dependencies, which are referred to as: resource conflicts, procedural dependencies, and data dependencies. Resource conflicts occur when two instructions executing in parallel tend to access the same resource, e.g., the system bus. Data dependencies occur when the completion of a first instruction changes the value stored in a register or memory, which is later accessed by a later completed second instruction.
During execution of instructions, an instruction sequence may fail to execute properly or to yield the correct results for a number of different reasons. For example, a failure may occur when a certain event or sequence of events occurs in a manner not expected by the designer. Further, a flaw in the design of a circuit or logic equation may cause an error. Due to the complexity of designing an out-of-order processor, the processor design may logically mis-process one instruction in combination with another instruction, causing an error. In some cases, a selected frequency, voltage, or type of noise may cause an error in execution because of a circuit not behaving as designed. Errors such as these often cause the scheduler in the microprocessor to “hang,” resulting in execution of instructions coming to a halt.
Therefore, it would be advantageous to have a method and apparatus for properly detecting errors causing a microprocessor, in particular an SMT processor, to hang.